Ports and I/O Devices

The CHROMAtrs from South Shore Computer Concepts (later Micro Control Systems) is a color graphics, sound, and joystick add-on for the TRS-80. Its heart is the Texas Instruments TMS9918A Video Display Processor - the same VDP used in the ColecoVision, TI-99/4A, MSX, and Sega SG-1000 - giving up to 256x192 resolution, 16 colors, and 32 hardware sprites. The board plugs into the expansion bus and occupies the 78H-7FH port block; the base address is jumper-selectable to any multiple of 8 (00H, 08H, ... 78H) to avoid conflicts. The port assignments below were determined by disassembly of the CHROMA/CMD driver (loaded at E400H); addresses cited refer to that driver.

Note: Because the CHROMAtrs sits on the expansion bus, on a Model III or Model 4 the external I/O bus must be enabled before its ports respond. The driver does this by setting bit 4 of Port ECH (OUT (0ECH),10H at 0E400H), the same enable used by the NewClock-80 - see the Port ECH / Model III and Model 4 notes. On a Model I the bus is always live and no enable is needed.

The Alpha Products NewClock-80 (released 1983, replacing the earlier TIMEDATE 80 and remaining software compatible with it) is a battery-backed clock/calendar built around an OKI MSM5832 real-time-clock chip. It plugs into the expansion bus and requires no hardware modifications. The same board design is used on the Model I, Model III, and Model 4; only the I/O-bus enable step differs (see the Model III/4 entry).

The clock presents the time and date as 13 read/write ports, one BCD digit per port. Each port returns its digit in the low nibble (bits 0-3); the upper four bits are undefined and must be masked off with AND 15 (or AND 3 for the capped tens digits). Early boards pull the unused high bits low, so reads return 0-15; later boards may leave them high, returning 240-255. Masking makes code work on both.

High Port / Low Port

The NewClock-80 is jumper-selectable between two port ranges so it can coexist with other peripherals. Both ranges expose the identical register set, bit layout, and masking - only the base address differs:

• High Port - ports 176-188 (B0H-BCH). This is the factory default and the range used by the PORTHELP tutorial and most Alpha Products driver software.
• Low Port - ports 112-124 (70H-7CH). This is the range used by the predecessor TIMEDATE 80 clock, which the NewClock-80 replaced while staying software compatible. Drivers that support both configurations detect the clock and add an offset of 0 (Low) or 64 (High) to a base of 112.

The register map below lists the Low Port address first, then the High Port address. The examples further down assume a High Port clock; for a Low Port clock, subtract 64 from each port number (e.g. read seconds-ones from 112 instead of 176).

Register Map (Low Port 112-124 / High Port 176-188)

Status Bits

Three extra status bits are packed into two of the ports:

• Leap-Year bit - Port 184 (B8H), bit 2: LEAP = INP(184) AND 4. Returns 4 if next February has 29 days, 0 otherwise. The day-tens digit is read with AND 3 to mask this bit off.
• 12/24-hour mode bit - Port 181 (B5H), bit 3: MODE = INP(181) AND 8. Returns 8 for 24-hour mode, 0 for 12-hour mode.
• AM/PM bit - Port 181 (B5H), bit 2: AMPM = INP(181) AND 4. In 12-hour mode, returns 4 for PM and 0 for AM. Meaningless in 24-hour mode.

A driver can also test for the clock's presence by reading the day-tens port (120 Low / 184 High): a value greater than 127 indicates no clock is installed at that range.

Reading the Clock (Examples)

The parentheses around every (15 AND INP(...)) term are mandatory because of BASIC's order of operations.

Setting the Clock

The same ports accept OUT to set the time and date - for example OUT 179, MIN/10 then OUT 178, MIN-INT(MIN/10)*10. Two cautions:

• Seconds cannot be set. Any OUT to ports 177 or 176 resets the seconds to zero regardless of the value sent.
• The hour-tens port carries the mode bits. When writing port 181 you must OR in the desired 12/24 and AM/PM bits along with the hour-tens digit, e.g. OUT 181, HOURMODE OR AMPM OR (HOUR/10) then OUT 180, HOUR-INT(HOUR/10)*10.

Note: On a Model I the clock ports are always live and need no enabling. On a Model III or Model 4 the external I/O ports must be enabled first - see the NewClock-80 entry under Ports (Model III and Model 4).

The Orchestra-80 (1980) and Orchestra-85 (1981) were music synthesizer add-ons for the TRS-80 Model I, designed by Jon Bokelman and sold by Software Affair. Both plug into the expansion bus. Each output port is a simple 8-bit digital-to-analog converter: the playback routine repeatedly writes successive sample values to the port(s) in a tight timed loop, generating the waveform directly. (The Model III / Model 4 equivalent is the Orchestra-90, which uses ports 75 and 79 - see the Model III and Model 4 section.)

Note: The Orchestra-85's stereo ports (B5H, B9H) fall within the same B0H-BCH block used by the NewClock-80. The two devices cannot share that port range simultaneously; a NewClock-80 would need to be set to its Low Port (112-124 / 70H-7CH) configuration to coexist with an Orchestra-85.

The SPRINTER III was controlled both by a jumper on the card and a software switch. The jumper on the card set the speed multiplier and that was the only way to control that. The software control was just on (high) or off (low).

The Orchestra-90 is a pair of simple 8-bit digital-to-analog converters - one per stereo channel, with no command, status, or control registers

Each channel's output is the sum of the currently sounding voices: the player accumulates the active voice samples in the accumulator (ADD A,(HL) per voice) and then writes the mixed byte to that channel's port. The two ports are written one after the other

Note: During playback the driver also manipulates port ECH (the Model 4 control / wait-state register - LD A,10H : OUT (0ECH),A and runs with interrupts disabled. This is timing setup for the cycle-counted sample loop, not a function of the Orchestra-90 hardware itself

The Memory Merchant Shuffleboard III (1981/1982) is a plug-in board that adds a full 64K CP/M 2.2 environment to the Model III. It plugs into the Z-80 socket and one nearby socket with no cut traces or soldering, supplying an onboard Z-80A, 16K of RAM, and a CP/M boot ROM. The board is controlled entirely by writing a single map byte to output port 7FH (127), which reconfigures the Model III's memory map between native TRS-80 and CP/M layouts.

Although three bits give eight combinations, only four map-byte values are used:

The Model III High-Resolution Graphics Board operates using port-mapped addressing and is based on the MC6845 CRTC chip.

The Grafyx Solution is a third-party high-resolution graphics board from Micro-Labs, Inc., and is not the Radio Shack graphics board documented above; the two are competing products that happen to share the 80H-8FH port region. On the Model 4 it gives a maximum resolution of 640 x 240 (153,600 individually accessible points) and carries 20,480 bytes of its own read/write memory that does not occupy the TRS-80 address space — 19,200 bytes hold the 640 x 240 bitmap (saved as 75 consecutive 256-byte records) and the remaining 1,280 bytes are free for the user. Because the board's memory is reached only through the X/Y address ports rather than being memory-mapped, it does not conflict with normal TRS-80 RAM.

The board is programmed entirely through four consecutive ports. The manual documents these in decimal (the values used by the BASIC OUT and INP statements); the hexadecimal equivalents are shown for cross-reference.

Control register (port 131 / 83H) bit map: Each function has a "sum value"; add the sum values of every bit you want ON to get the value to output. An asterisk (*) marks an active-low/complemented function as named in the manual.

Setting the right bits lets the X and/or Y address auto-increment or auto-decrement after each data read and/or write, so a horizontal or vertical run of bytes can be written without re-sending the address each time. For example, to auto-increment X after every write in 640 x 240 mode, turn on bits 0, 1, 4, 5, and 7, giving 1+2+16+32+128 = 179.

Common control values:

The three basic modes — Normal, hi-res with text overlay, and hi-res with text off — are selected by the two least-significant bits of the control byte. Pressing the orange reset key also forces the board back to Normal Display mode. The contents of graphics memory are preserved across mode changes, so a picture re-appears when hi-res is re-enabled.

The Alpha Products NewClock-80 uses the identical port set and bit layout on the Model III and Model 4 as it does on the Model I - the High Port configuration occupies ports 176-188 (B0H-BCH), one BCD digit per port, each masked with AND 15 (or AND 3 for the capped tens digits). For the full register map, status-bit definitions, and read/set examples, see the NewClock-80 entry under Ports (Model I). The Model III version of the board also works in the Model 4.

Enabling the Ports (Model III and Model 4)

Unlike the Model I, the Model III and Model 4 do not expose the external I/O bus by default. Before any INP or OUT to the NewClock-80 ports will work, the external I/O bus must be enabled by setting bit 4 of Port ECH (236 decimal). From BASIC:

That enables the ports until the next OUT 236 clears the bit. BASIC re-issues an OUT 236 each time a program exits to the >_ prompt, which disables them again. To stop BASIC from doing this, on a Model III you can:

Do not execute that POKE on a Model I. Because Port ECH also controls cassette, video, character set, and (on the Model 4) CPU clock speed, drivers should read the current ECH shadow value, OR in only bit 4, and write the whole byte back rather than overwriting the other control bits. See the Port ECH entry for the full bit map.

Assembly-Language Enable

In machine code the same enable is done by OR-ing bit 4 (10H) into the cached ECH control byte and writing it out. On the Model III the ECH shadow is kept at 4210H; on the Model 4 it is at 0076H. For example (Model III):

LD   A,(4210H)   ; current ECH control byte
OR   10H         ; set bit 4 (enable I/O bus)
LD   (4210H),A   ; update the shadow
OUT  (0ECH),A    ; enable external I/O ports

The clock digits are then read with IN A,(C) stepping C down through the port addresses, masking each nibble (AND 0FH, or AND 03H for the day-tens and hour-tens digits) and combining the tens and ones digits into a BCD value.

Network 4 uses an Omninet RS-422 network interface (the Corvus Transporter chip). The four ports D0–D3 serve overlapping dual roles depending on read vs. write direction and the current state of the Transporter's internal 16-bit address pointer. Port equates and all behavioural detail below are confirmed by the Network 4 Transporter ROM disassembly (ROM Version 01.01.00).

Boot-time initialization sequence:

1. Port ECH bit 4 is set to enable the I/O bus: the byte at RAM address 4210H is OR'd with 10H and written back to ECH, then stored.
2. The Transporter is reset: address pointer is set to 0 (OUT 00H to D1H, then D3H), FFH is written as the response code (OUT to D0H), then 20H (ASCII space = Reset Command) followed by three zero bytes for the response address. A strobe is issued to station address 1, then OMWAIT is called with A=0 to wait for the response at zero-page offset 0. The returned value in A is this station's Transporter address.
3. If the address equals 63H (ASCII '?') the machine is the network server and jumps to the hard-disk boot path (SERVR). Otherwise it reads the boot-pointer sector over the network (OREAD routine, 8 retries with random back-off on error) and loads the appropriate boot volume.

Special flag at address 6FF0H: On startup the ROM reads the 16-bit word at 6FF0H and compares it with 5041H (ASCII 'PA'). If they match, the WAITR delay routine runs for approximately 4 seconds (inner loop counts 1–65536, outer loop repeats 32 times) to protect against rapid power-cycling. After the flag check, DE (= 5041H) is written to 6FF0H to set the flag for the next boot. Once the boot file has been fully loaded, the two-byte start address extracted from the load record is written back to 6FF0H, clearing the flag, and execution jumps there.

Note: A Model I will set itself up based on the switches on the card. A Model III will default to 300 baud, 8 Bit Word, 1 Stop Bit, and No Parity.

A quick note on Bit 5 (thanks to George Phillips). Bit 5 of Port ECH is supported on both the Model III and Model 4 and is set to ENABLE at 345CH. There is a latch connected to this bit that always has the current value. This latch has a wire connecting to both the Z-80 bus and the video circuitry which which mediates acccess to video RAM, so the processing of this bit is actually handled by separate hardware and not the ROM.

An example of this bit can be shown via the short program 10 CLS:FORI=0TO1023:POKE15360+I,191:NEXT. If run once with POKE 16912,0 and run again with POKE 16912,32, hash lines as the screen refreshes can be seen in one but not the other.

The Seatronics Super Speed-Up Board uses bits 6 and 7 of ECH to select the Z-80 Clock Rate: