Ports and I/O Devices

Page Index

Ports (Model I)

Block 78-7F - ChromaTRS

Block B0-BC - NewClock-80

EBH - Serial Port

			IN                                OUT
			(Input Data)                      (Output Data)
B7:	Data-7                            Data-7
B6:	Data-6                            Data-6
B5:	Data-5                            Data-5
B4:	Data-4                            Data-4
B3:	Data-3                            Data-3
B2:	Data-2                            Data-2
B1:	Data-1                            Data-1
B0:	Data-0                            Data-0


EAH:	Serial Port
			IN                                OUT
			(Uart Status bits)                (Uart parameters set)
B7:	1=Data Available                  1=Even Parity
B6:	0=Data sent (TBMT)                WD Lngth 00=5 01=7
B5:	1=Overrun Error                   WD Lngth 10=6 11=8
B4:	1=Framing Error                   0=1-Stop bit
B3:	1=Parity Error                    1=No Parity
B2:	unused                            1=Transmit Enable
B1:	unused                            0=DTR on
B0:	unused                            0=RTS on


E9H:	Serial Port
			IN                                OUT
			(DIP Switches??)                  (Set speeds)
B7:	Parity 0=Odd                        Set Baud rate (all bits)
B6:	Wd Length 00=5 01=7                 Bits 0-3 = Receive Speed
B5:	          10=6 11=8                 Bits 4-7 = Transmit Speed
B4:	Stop bits 0=1 1=2                     50 = 00H        75 = 11H
B3:	Parity 0=enable                       100 = 22H    134.5 = 33H
B2:	unused                                150 = 44H      300 = 55H
B1:	unused                                600 = 66H    1,200 = 77H
B0:	unused                              1,800 = 88H    2,000 = 99H
			                            2,400 = AAH    3,600 = BBH
			                            4,800 = CCH    7,200 = DDH
			                            9,600 = EEH   19,200 = FFH


E8H:	Serial Port
			IN                                OUT
			(Signals Input)                   (Reset Uart)
B7:	CTS                               Any value will reset the
B6:	DSR                               Uart
B5:	0=Carrier Detected
B4:	1?=Ring Indicate
B3:	unused
B2:	unused
B1:	unused
B0:	Serial data input

Ports (Model III and Model 4)

Note: Tandy tended to allocate ports in groups of 4.

Orch-90:

Port	Use
75	ORCH-90
79	ORCH-90

Graphics Board (Model 4 ONLY):

Port	Use
80H	Input: Reserved. Output: Graphics board register
81H	Input: Graphics board RAM read. Output: Graphics board RAM write.
82H	Input: Reserved. Output: Graphics board Y register.
83H	Input: Reserved. Output: Graphics board X register.
84H	Mod 4 - various controls. 80 micro, March 84, p. 122. Input is reserved. Output: Bits 0-1: Video memory, keyboard memory, and Model III ROM. 00: Model III ROMs Enabled, Video/Keyboard = Model 3 10: Model III ROMs Disabled, Video/Keyboard = Model 3 01: Model III ROMs Disabled, Video/Keyboard = Model 4 (In) 10: Model III ROMs Disabled, Video/Keyboard = Model 4 (Out) Bit 2: Video display mode (0 = 64x16, 1 = 80x24). Bit 3: Reverse Video. Bits 4-6: RAM bank select 000: Lower 32K Ram in Bank 0, Upper 32K RAM in Bank 1 010: Lower 32K Ram in Bank 0, Upper 32K RAM in Bank 2 011: Lower 32K Ram in Bank 2, Upper 32K RAM in Bank 1 110: Lower 32K Ram in Bank 0, Upper 32K RAM in Bank 3 111: Lower 32K Ram in Bank 3, Upper 32K RAM in Bank 1 Bit 7: Video page select (64x16 mode): 0 = page 0, 1 = page 1.
85H-87H	Same as 84H.

Block 88/89/8A/8B - CRT Control

Port	Use
88H	CRT controller control register.
89H	CRT controller data register.
8AH	CRT controller control register.
8BH	CRT controller data register.

Block 8C/8D/8E/8F - Graphics Board:

Port	Use
8CH-8FH	Graphics board select 2.

Block 90/91/92/93 - Sound Port (Model 4 ONLY):

Port	Use
90H	Model 4 sound port. Any of the sound routines used on the Model I and Model III that uses port FFH can be changed to this and then the Model IV's built in speaker can be used!. Only BIT 0 was used for output, 0=Low, 1=High.
91H-93H	Same as 90H.

Reserved:

Port	Use
94H-BFH	Reserved.

Model 4P Boot ROM (Model 4P Only):

Port	Use
9CH	Switch the Model 4P Boot ROM in or OUT. Output: 0: Switch the Model 4P Boot ROM out 1: Switch the Model 4P Boot ROM in

ARCNET (Model 4P Only):

Port	Use
B6H	Arcnet Board (Input/Output).

Hard Drive:

Port	Use
C0H	Write Protection. Write/Output: Reserved. Read/Input: Hard disk write protect: Bit 0 (INTRQ): Interrupt Request Bit 1 (HWPL): If set, at least one hard drive is currently write protected Bit 4 (WPD4): If set, hard drive 4 is currently write protected Bit 5 (WPD3): If set, hard drive 3 is currently write protected Bit 6 (WPD2): If set, hard drive 2 is currently write protected Bit 7 (WPD1): If set, hard drive 1 is currently write protected
C1H	Hard disk controller board control register (Read/Write). Bit 2: RUMORED to enable wait state support on a 8X300 Controller Board Bit 3: If set, enable controller Bit 4: If set, reset controller
C2H-C3H	Model II with 8x300 Controller - Hard disk device ID register. Output: Reserved. Input: Hard disk device ID register.
C4H	Model II with 8x300 Controller - Hard disk CTC channel 0.
C5H	Model II with 8x300 Controller - Hard disk CTC channel 1.
C6H	Model II with 8x300 Controller - Hard disk CTC channel 2.
C7H	Model II with 8x300 Controller - Hard disk CTC channel 3.
C8H	Hard Disk Data Register (Read/Write). Register 0 for WD1010 Winchester Disk Controller Chip.
C9H	Hard Disk Write Pre-Comp Cyl. Register 1 for WD1010 Winchester Disk Controller Chip. Write/Output: The RWC start cylinder number = The value stored here divide by 4. Read/Input: Error Register: Bit 0: Per the WD1010-00 Spec Sheet, this is DAM Not Found. The Radio Shack 15M HD Service Mauals says that this bit is reserved and forced to 0 Bit 1: Track 0 Error (Restore Command) Bit 2: Aborted Command Bit 4: ID Not Found Error Bit 5: CRC Error - ID Field Bit 6: CRC Error - Data Field Bit 7: Bad Block Detected
CAH	Hard Disk Sector Count (Read/Write). Register 2 for WD1010 Winchester Disk Controller Chip. This is used only for multiple sector access. Internally decrements when used.
CBH	Hard Disk Sector Number (Read/Write). Register 3 for WD1010 Winchester Disk Controller Chip.
CCH	Hard Disk Cylinder LSB (Read/Write). Register 4 for WD1010 Winchester Disk Controller Chip.
CDH	Hard Disk Cylinder MSB (Read/Write). Register 5 for WD1010 Winchester Disk Controller Chip. Since the maximum number of cylinders is 1024, only Bits 0 and 1 are used (1023 = 0000 0011 + 1111 1111).
CEH	Hard Disk Sector Size / Drive # / Head # (Read/Write). Register 6 for WD1010 Winchester Disk Controller Chip. Bits 0-2: Head Number (0-7) Bits 3-4: Drive Number (00=DSEL1, 01=DSEL2, 10=DSEL3, 11=DSEL 4) Bits 5-6: Sector Size (00=256, 01=512, 10=1024, 11=128) Bit 7: Extension (if this is set, Error Checking and Correction codes are in use and the R/W data [sector length + 7 bytes] do not check or generate CRC)
CFH	Hard Disk Error Status Register (Read Only). Register 7 for WD1010 Winchester Disk Controller Chip. Read = Status Register: Bit 0: Error Exists (just an OR of Bits 1-7) Bit 1: Command in Progress Bit 2: Reserved (so forced to 0) Bit 3: Data Request Bit 4: Seek Complete Bit 5: Write Fault Bit 6: Drive Ready Bit 7: Busy Write = Command Register.

|--------------------------------------------------------------------------|
|PORT CFH - WRITE - Command Register Instruction Set                      |
|         Bits: 7 6 5 4 3 2 1 0    |           Bits: 7 6 5 4 3 2 1 0      |
| Restore      | 0 0 0 1 d c b a    | Read Sector    | 0 0 1 0 i m 0 0    |
| Seek         | 0 1 1 1 d c b a    | Write Sector   | 0 0 1 1 0 m 0 0    |
| Scan ID      | 0 1 0 0 0 0 0 0    | Write Format   | 0 1 0 1 0 0 0 0    |
|                                  |                                      |
| "dcba" defines step rate field:  | "i" defines interrupt enable status: |
|    0000 =  35 us.                |   0 = interrupt when data request    |
| 0001-1111 =  0.5-7.5 ms in       |         line (DRQ*) is enabled       |
|            0.5 ms steps          |   1 = interrupt at end of command    |
|                                                                         |
| "m" defines multiple sector flag: 0 = one sector, 1 = multiple sectors  |
`-------------------------------------------------------------------------'
* The 4P ROM is known to send three commands to this port: 16H-restore, 20H-read one sector, 70H-seek

Block D0/D1/D2/D3 - Network 4:

Port	Use
D0H	Input/Output with Automatic Increment
D1H	Omninet Pointer: LSB
D2H	Input without Automatic Increment. Also an Omninet Strobe Point.
D3H	Omninet Pointer: MSB

Interrupts:

Port	Use
E0H	Maskable Interrupt Bit 0 - 3365H (Cassette Routine with E set to HIGH; Rising Edge Interrupt) Bit 1 - 3669H (Cassette Routine with E set to LOW; Falling Edge Interrupt) Bit 2 - 4046H (Real Time Clock Interrupt) Bit 3 - 403DH (I/O Bus Interrupts) Bit 4 - 4206H (RS-232 Transmitter) Bit 5 - 4209H (RS-232 Receiver) Bit 6 - 4040H (RS-232 Error) Bit 7 - 4043H Inputting from each bit would be 0=False, 1=True. Outputting to each bit would be 0=Disable, 1=Enable.
E4H	Select NMI options/read NMI status: Input: Bit 5: Reset Status (0 = False, 1 = True) Bit 6: DRQ Status (0 = False, 1 = True) Bit 7: INTRQ Status (0 = False, 1 = True) Output: Bit 6: Enable or Disable DRQ Interrupt (0 = Disable, 1 = Enable) Bit 7: Enable or Disable INTRQ Interrupt (0 = Disable, 1 = Enable)

Block E8/E9/EA/EB - RS-232:

Note: A Model I will set itself up based on the switches on the card. A Model III will default to 300 baud, 8 Bit Word, 1 Stop Bit, and No Parity.

Port	Use
E8H	RS-232 Status Register and Master Reset: Output: Any byte will reset the RS-232 Input: Bit 0 - Copy of serial input pin UART (Pin 20 of the DB-25) Bit 1 - UART Control Register (0=Disable, 1=Enable) Bit 4 - Ring Indicator (Pin 22 of the DB-25) Bit 5 - Carrier Detect (Pin 8 of the DB-25) Bit 6 - Data Set Ready (Pin 6 of the DB-25) Bit 7 - Clear to Send (Pin 5 of the DB-25)
E9H	RS-232 Baud Rate Select and Sense Switches: Output: 0000 0000 (00H) - Baud: 50 0001 0001 (11H) - Baud: 75 0010 0010 (22H) - Baud: 100 0011 0011 (33H) - Baud: 134.5 0100 0100 (44H) - Baud: 150 0101 0101 (55H) - Baud: 300 0110 0110 (66H) - Baud: 600 0111 0111 (77H) - Baud: 1,200 1000 1000 (88H) - Baud: 1,800 1001 1001 (99H) - Baud: 2,000 1010 1010 (AAH) - Baud: 2,400 1011 1011 (BBH) - Baud: 3,600 1100 1100 (CCH) - Baud: 4,800 1101 1101 (DDH) - Baud: 7,200 1110 1110 (EEH) - Baud: 9,600 1111 1111 (FFH) - Baud: 19,200 Input (used only on the Model I as it reads the dip switches): Bit 0-2 = Baud Rate Select (50-1200; 5=300 Baud; 7=1200 Baud) Bit 4 = Parity (0 = Enabled, 1 = Disabled) Bits 5-6 = Word Length Select (00 = 5, 01=6, 10=7, 11=8) Bit 7 = Parity (0 = Odd, 1 = Even)
EAH	RS-232 UART Control Register and Status Register: Input: Bits: 0-2 = Unused Bit 3: Parity Error (1=True) Bit 4: Framing Error (1=True) Bit 5: Overrun Error (1=True) Bit 6: Data Sent (1=True) Bit 7: Data Ready (1=True) Output: Bit 0: Data Terminal Ready (1=DTR Off) (Pin 20 of the DB-25) Bit 1: Request to Send (1=RTS Off) (Pin 4 of the DB-25) Bit 2: Break (1=Send Break Signal) Bit 3: Parity Enable (0 = Enable Parity, 1 = Disable Parity) Bit 4: Stop Bits (0 = 1 Stop Bit, 1 = 2 Stop Bits) Bits 5-6: Select Word Length (00 = 5, 01 = 7, 10 = 6, 11 = 8) Bit 7: Parity (0 = Odd, 1 = Even)
EBH	RS-232 Register: Input: Received Data Output: Transmit Data

Port Add.! D7  ! D6  ! D5  ! D4  ! D3  ! D2  ! D1  ! D0  !
=========!=====!=====!=====!=====!=====!=====!=====!=====!
E8 Write ! <---- UART  RESET & INITIALIZATION ONLY ----->!
         !           NO  DATA  BITS  REQUIRED            !  T
---------!-----!-----!-----!-----!-----!-----!-----!-----!
E8 Read  ! cts ! dsr ! cd  ! ri  !  -  !  -  ! rec !  -  !
         !     !     !     !     !     !     ! i/p !     !  R
=========!=====!=====!=====!=====!=====!=====!=====!=====!
E9 Write !   Software Baud rate settings  (see manual)   !
         !     !     !     !     !     !     !     !     !  S
---------!-----!-----!-----!-----!-----!-----!-----!-----!
E9 Read  !Parit! w/l ! w/l ! stop!Parit! Baud! Baud! Baud!
switches !ev/od!slct1!slct2! 1or2!en/di!  1  !  2  !  3  !
=========!=====!=====!=====!=====!=====!=====!=====!=====!  I
EA Write !Parit! w/l ! w/l ! stop!Parit! TX  ! DTR ! RTS !
control  !ev/od!slct1!slct2! 1or2!en/di!en/di!     !     !
---------!-----!-----!-----!-----!-----!-----!-----!-----!
EA Read  ! DAV ! TBMT!o/run!frame!Parit!  -  !  -  !  -  !  8
 Uart    !     !     !error!error!error!     !     !     !
=========!=====!=====!=====!=====!=====!=====!=====!=====!
EB Write ! <---------- 8 BIT DATA  to  UART -----------> !
EB Read  ! <---------- 8 BIT DATA from UART -----------> !
========='====='====='====='====='====='====='====='====='---
		   D7    D6    D5    D4    D3    D2    D1    D0
=========v=====v=====v=====v=====v=====v=====v=====v=====v---
F8 Write !  -  !  -  !  -  !  -  !  -  !Uart ! DTR ! RTS !  S
         !     !     !     !     !     !Reset!     !     !
---------!-----!-----!-----!-----!-----!-----!-----!-----!  Y
F8 Read  ! <---------- 8 BIT DATA from UART -----------> !
         !     !     !     !     !     !     !     !     !  S
=========!=====!=====!=====!=====!=====!=====!=====!=====!
F9 Write ! <---------- 8 BIT DATA  to  UART -----------> !
         !     !     !     !     !     !     !     !     !  8
---------!-----!-----!-----!-----!-----!-----!-----!-----!
F9 Read  !TMBT ! CTS ! DSR ! CD  ! PE  ! FE  ! OR  ! DAV !  0
         !     !     !     !     !     !     !     !     !
========='====='====='====='====='====='====='====='====='

Misc:

Port	Use
ECH	Write = various controls/ read = reset clock Bit 0: Supposedly not used, but is on the Model III to test to see if the clock is on [0=off, 1=on]. Bit 1: Cass motor [0 = on, 1 = off] Bit 2: Double width [0 = normal, 1 = double] Bit 3: Alt. char. [0 = Kana, 1 = Misc] Bit 4: I/O bus [0 = disable, 1 = enable] Bit 5: Video waits [0 = disable, 1 = enable] Bit 6: CPU clock speed [0 = 2 mhz, 1 = 4 mhz] - Model 4 ONLY Bit 7: not used

A quick note on Bit 5 (thanks to George Phillips). Bit 5 of Port ECH is supported on both the Model III and Model 4 and is set to ENABLE at 345CH. There is a latch connected to this bit that always has the current value. This latch has a wire connecting to both the Z-80 bus and the video circuitry which which mediates acccess to video RAM, so the processing of this bit is actually handled by separate hardware and not the ROM.

An example of this bit can be shown via the short program 10 CLS:FORI=0TO1023:POKE15360+I,191:NEXT. If run once with POKE 16912,0 and run again with POKE 16912,32, hash lines as the screen refreshes can be seen in one but not the other.

The Seatronics Super Speed-Up Board uses bits 6 and 7 of ECH to select the Z-80 Clock Rate:

Bit 6	Bit 7	Speed
0	0	2 Mhz
1	0	4 Mhz
0	1	5.3 Mhz
1	1	8 Mhz

Floppy Drive:

Port	Use
F0H	FDC Command/Status: Input (depends on what the inquiry is in relation to: I=Restore, Seek, and Step, II = Read/Write Sector, III = Read/Write Track and Read Address: Bit 0: [I] BUSY = HIGH indicates command in progress [II/III] Busy = HIGH indicates command Is under execution. Bit 1: [I] INDEX = HIGH indicates index mark detected from drive [II/III] DATA REQUEST = HIGH indicates index mark detected from drive. Bit 2: [I] TRACK 0 = HIGH indicates Read/Write head is positioned to Track 0 [II/III] LOST DATA = HIGH indicates the computer did not respond to DRQ in one byte time. Bit 3: [I] CRC ERROR = HIGH indicates a CRC error was found in the ID field [II/III] CRC ERROR = If BIT 4 is set, an error is found in one or more ID fields otherwise it indicates error in data field. Bit 4: [I] SEEK ERROR = HIGH indicates the desired track was not verified [II/III] RECORD NOT FOUND = HIGH indicates the desired track, sector, or side were not found. Bit 5: [I] HEAD LOADED = HIGH indicates the head is loaded and engaged [II/III] RECORD TYPE/WRITE FAULT = On Read Record, HIGH indicates the record-type code from data field address mark (1: Deleted Data Mark, 0: Data Mark). On any write, HIGH indicates a Write Fault. Bit 6: [I] PROTECTED = HIGH indicates Write Protect is activated [II/III] PROTECTED = On Read Record or Read Track, not used. On any write: it indicates a Write Protect. Bit 7: NOT READY = HIGH indicates the drive is not ready Output: Bits 765 \| 4 \| 3 \| 2 \| 1 0 00-0F: 000 \| 0 \| h \| V \| R R = Restore 10-1F: 000 \| 1 \| h \| V \| R R = Seek 20-3F: 001 \| T \| h \| V \| R R = Step 40-5F: 010 \| T \| h \| V \| R R = Step In 60-7F: 011 \| T \| h \| V \| R R = Step Out 80-9E: 100 \| m \| S \| E \| C 0 = Read Sector A0-BF: 101 \| m \| S \| E \| C A = Write Sector C0,C4: 110 \| 0 \| 0 \| E \| 0 0 = Read Address D0-DF: 110 \| 1 \| x \| x \| x x = Force Interrupt E0,E4: 111 \| 0 \| 0 \| E \| 0 0 = Read Track F0,F4: 111 \| 1 \| 0 \| E \| 0 0 = Write Track Legend: RR = Stepping Motor Rate (00=6ms, 01=12ms, 10=20ms, 11=30ms) h = Head Load Flag (1: load head at beginning, 0: unload head) V = Track Number Verify Flag (0: no verify, 1: verify on dest track) T = Track Update Flag (0: no update, 1: update Track Register) A = Data Address Mark (0: FB, 1: F8 (deleted DAM)) C = Side Compare Flag (0: disable side compare, 1: enable side comp) E = 15 ms delay (0: no 15ms delay, 1: 15 ms delay) S = Side Compare Flag (0: compare for side 0, 1: compare for side 1) m = Multiple Record Flag (0: single record, 1: multiple records) xxxx = Interrupt Condition Flags (1111 = Immediate interrupt, Index pulse, Ready to not ready transition, Not ready to ready transition) Output Examples: 00H: Restore 80H (1000 0000): Read single sided single sector A0H (1010 0000): Write single normal sector A1H (1010 0001): Write single sector read protect C0H (1100 0000): Read address, no delay D0H (1101 0000): Reset; puts FDC in mode 1 (INTRQ; "000" terminate command without interrupt) E0H (1110 0000): Read track, no delay F0H (1111 0000): Write track, no delay
F1H	FDC Track Register (regardless if READ or WRITE)
F2H	FDC Sector Register (regardless if READ or WRITE)
F3H	FDC Data Register (the data byte to be read or WRITTEN to disk)
F4H	Select drive and options. Output: Bit 0: Drive 0 Select Bit 1: Drive 1 Select Bit 2: Drive 2 Select Bit 3: Drive 3 Select Bit 4: Side Select (0 = Select Side 0, 1 = Select Side 1) Bit 5: Write Precompensation (0 = Disable WP, 1 = Enable WP) Bit 6: Wait State Generation (0 = Disable WSG, 1 = Enable WSG) Bit 7: Density Select (0 = Single/FM, 1 = Double/MFM)

Block F8/F9/FA/FB - Printer:

Port	Use
F8/F9/FA/FB	Line printer address port: Input: Bit 4: No Printer Fault Bit 5: Device Select Bit 6: Not Out of Paper Bit 7: Not Busy Output: Data to print

Block FC/FD/FE/FF - Cassette:

Port	Use
FC/FD/FE/FF	Cassette port: Input: Bit 7: Data Bit (0 = Low, 1 = High) Output: Bits 0-1: 00=0.85 Volts, 10=0.0 Volts, 01 = 0.46 Volts

Address	Use
3000-37DF	NO MEMORY here at all
37E0	Disk drive select latch
37E1-37EF	TRSDOS v2.3 Disk Registers
37E4	Cassette drive latch (Select Cassette Drive)
37E8	Line printer data port when storing
37E8	Line printer status port when loading
37EC	Disk command register when storing
37EC	Disk status register when loading
37ED	Disk track register
37EE	Disk sector register
37EF	Disk data register
3801-3880	Keyboard memory
3C00-3FFF	Video display memory